Performance and Reliability Enhancement Techniques for Two Dimensional Network-on-Chips using Adaptive Deflection Routers

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Performance and Reliability Enhancement Techniques for Two Dimensional Network-on-Chips using Adaptive Deflection Routers

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dc.contributor.author Simi Zerine Sleeba
dc.contributor.author Dr. Mini M.G.
dc.date.accessioned 2019-02-28T05:20:41Z
dc.date.available 2019-02-28T05:20:41Z
dc.date.issued 2017-12-22
dc.identifier.uri http://dyuthi.cusat.ac.in/purl/5318
dc.language.iso en en_US
dc.publisher Cochin University of Science and Technology en_US
dc.subject Network on Chip en_US
dc.subject Permutation Deflection Network en_US
dc.title Performance and Reliability Enhancement Techniques for Two Dimensional Network-on-Chips using Adaptive Deflection Routers en_US
dc.type Thesis en_US


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